AD5544ARS datasheet(16/20 Pages) AD

16 / 20 page

AD5554/AD5554

Rev. A | Page 16 of 20

SERIAL DATA INTERFACE

The AD5544/AD5554 uses a 3-wire (CS, SDI, CLK) SPI compa-

tible serial data interface. Serial data of AD5544 and AD5554 is

clocked into the serial input register in an 18-bit and 16-bit

data-word format respectively. MSB bits are loaded first. Table 6

defines the 18 data-word bits for AD5544.

Table 7 defines the 16 data-word bits for AD5554. Data is placed

on the SDI pin, and clocked into the register on the positive

clock edge of CLK subject to the data setup and data hold time

requirements specified in the interface timing specifications.

data can only be clocked in while the CS chip select pin is active

low. For AD5544, only the last 18 bits clocked into the serial

logic high state, extra data bits are ignored. For AD5554, only

the last 16 bits clocked into the serial register will be inter-

rogated when the CS pin returns to the logic high state. Since

most microcontrollers output serial data in 8-bit bytes, three

right justified data bytes can be written to the AD5544. Keeping

the CS line low between the first, second, and third byte trans-

fers will result in a successful serial register update. Similarly,

two right justified data bytes can be written to the AD5554.

Keeping the CS line low between the first and second byte

transfer will result in a successful serial register update.

Once the data is properly aligned in the shift register, the posi-

tive edge of the CS initiates the transfer of new data to the target

DAC register, determined by the decoding of address Bits A1

and A0. For AD5544, Table 5, Table 7, Table 9, and Figure 4

define the characteristics of the software serial interface. For

AD5554, Table 6, Table 8, Table 9, and Figure 5 define the

characteristics of the software serial interface. Figure 29 and

Figure 30 show the equivalent logic interface for the key digital

control pins for the AD5544. AD5554 has a similar configura-

tion, except it has 14 data bits. Two additional pins, RS and

MSB, provide hardware control over the preset function and

DAC register loading.

INPUT

DAC A

2:4

DECODE

D10

D11

D12

D13

D14

D15

DAC D

DAC C

DAC B

DAC A

POWER-

RESET

DAC B

DAC C

DAC D

DAC A

AD5544

VREFA B C D

VDD

RFBA

IOUTA

AGNDA

RFBB

IOUTB

AGNDB

RFBC

IOUTC

AGNDC

RFBD

IOUTD

AGNDD

AGNDF

DGND

MSB

VSS

SET

MSB

SET

MSB

SDO

SDI

CLK

LDAC

Figure 29. System Level Digital Interfacing

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