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551SPGGI8 Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # 551SPGGI8
Description  Low Skew 1 to 4 Clock Buffer
PDF  14 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

551SPGGI8 Datasheet(HTML) 6 Page - Renesas Technology Corp

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R31DS0038EU0204 Rev.2.04
Page 6
Aug 14, 2026
551S Datasheet
2.4.2
AC Electrical Characteristics
VDD = 3.3V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Operating Voltage
VDD
3.135
-
3.465
V
Input High Voltage, ICLK
VIH
[1]
1. Nominal switching threshold is VDD/2.
0.7xVDD
-
3.465
V
Input Low Voltage, ICLK
VIL
[1]
-
-
0.3xVDD
V
Input High Voltage, OE
VIH
0.7xVDD
-
VDD
V
Input Low Voltage, OE
VIL
-
-
0.3xVDD
V
Output High Voltage
VOH
IOH = -25mA
2.2
-
-
V
Output Low Voltage
VOL
IOL = 25mA
-
-
0.7
V
Operating Supply Current
IDD
No load, 135MHz
-
22
-
mA
Nominal Output Impedance
ZO
-
17
-
Ω
Input Capacitance
CIN
OE pin
-
5
-
pF
VDD = 1.8V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Frequency
5pF load [1]
1. With external series resistor of 33
Ω positioned close to each output pin.
-
-
200
MHz
Output Clock Rise Time
tOR
0.36 to 1.44V
-
0.6
1.0
ns
Output Clock Fall Time
tOF
1.44 to 0.36V
-
0.6
1.0
ns
Propagation Delay
135MHz [2]
2. With rail to rail input clock.
1.5
2
4
ns
Buffer Additive Phase Jitter, RMS
125MHz, Integration range:
12kHz–20MHz
-
0.03
0.05
ps
Output to Output Skew
Rising edges at VDD/2 [3]
3. Between any 2 outputs with equal loading.
-
50
65
ps
Start-up Time
tSTART-UP
Part start-up time for valid
outputs after VDD ramp-up
-
-
2
ms
Output Enable Time
tEN
CL < 5pF
-
-
3
cycles
Output Disable Time
tDIS
CL < 5pF
-
-
3
cycles



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