R31DS0038EU0204 Rev.2.04

Page 7

Aug 14, 2026

551S Datasheet

VDD = 2.5V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Frequency

5pF load [1]

1. With external series resistor of 33

Ω positioned close to each output pin.

-

-

200

MHz

Output Clock Rise Time

tOR

0.5 to 2.0V

-

0.6

1.0

ns

Output Clock Fall Time

tOF

2.0 to 0.5V

-

0.6

1.0

ns

Propagation Delay

135MHz [2]

2. With rail to rail input clock.

1.8

2.5

4.5

ns

Buffer Additive Phase Jitter, RMS

125MHz, Integration range:

12kHz–20MHz

-

0.035

0.05

ps

Output to Output Skew

Rising edges at VDD/2 [3]

3. Between any 2 outputs with equal loading.

-

50

65

ps

Start-up Time

tSTART-UP

Part start-up time for valid

outputs after VDD ramp-up

-

-

2

ms

Output Enable Time

tEN

CL < 5pF

-

-

3

cycles

Output Disable Time

tDIS

CL < 5pF

-

-

3

cycles

VDD = 3.3V ±5%, Ambient temperature -40° to +105°C, unless stated otherwise

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Frequency

5pF load [1]

1. With external series resistor of 33

Ω positioned close to each output pin.

-

-

200

MHz

Output Clock Rise Time

tOR

0.66 to 2.64V

-

0.6

1.0

ns

Output Clock Fall Time

tOF

2.64 to 0.66V

-

0.6

1.0

ns

Propagation Delay

135MHz [2]

2. With rail to rail input clock.

1.5

2

4

ns

Buffer Additive Phase Jitter, RMS

125MHz, Integration range:

12kHz–20MHz

-

0.037

0.05

ps

Output to Output Skew

Rising edges at VDD/2 [3]

3. Between any 2 outputs with equal loading.

-

50

65

ps

Start-up Time

tSTART-UP

Part start-up time for valid

outputs after VDD ramp-up

-

-

2

ms

Output Enable Time

tEN

CL < 5pF

-

-

3

cycles

Output Disable Time

tDIS

CL < 5pF

-

-

3

cycles