74HC_HCT00

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 7 — 25 November 2015

3 of 15

NXP Semiconductors

74HC00; 74HCT00

Quad 2-input NAND gate

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care.

7.

Limiting values

[1]

The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2]

For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.

For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.

Table 2.

Pin description

Symbol

Pin

Description

1A to 4A

1, 4, 9, 12

data input

1B to 4B

2, 5, 10, 13

data input

1Y to 4Y

3, 6, 8, 11

data output

GND

7

ground (0 V)

VCC

14

supply voltage

Table 3.

Function table[1]

Input

Output

nA

nB

nY

LX

H

XL

H

HHL

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

0.5

+7

V

IIK

input clamping current

VI < 0.5 V or VI >VCC +0.5 V

[1] -

20

mA

IOK

output clamping current

VO < 0.5 V or VO >VCC +0.5 V

[1] -

20

mA

IO

output current

0.5 V < V

O < VCC +0.5 V

-

25

mA

ICC

supply current

-

50

mA

IGND

ground current

50

-

mA

Tstg

storage temperature

65

+150

C

Ptot

total power dissipation

[2]

SO14, (T)SSOP14 and

DHVQFN14 packages

-

500

mW