74HC_HCT00

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Product data sheet

Rev. 7 — 25 November 2015

6 of 15

NXP Semiconductors

74HC00; 74HCT00

Quad 2-input NAND gate

[1]

tpd is the same as tPHL and tPLH.

[2]

tt is the same as tTHL and tTLH.

[3]

CPD is used to determine the dynamic power dissipation (PD in W):

PD =CPD  VCC2  fi  N+  (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

 (C

L  VCC

2

 f

o) = sum of outputs.

11. Waveforms

CPD

power dissipation

capacitance

per package; VI =GND to VCC

[3]

-22-

-

-

pF

74HCT00

tpd

propagation delay

nA, nB to nY; see Figure 6

[1]

VCC = 4.5 V

-

12

-

24

29

ns

VCC = 5.0 V; CL =15pF

-

10

-

-

-

ns

tt

transition time

VCC = 4.5 V; see Figure 6

[2]

-

--2922

ns

CPD

power dissipation

capacitance

per package;

VI =GND to VCC  1.5 V

[3]

-22-

-

-

pF

Table 7.

Dynamic characteristics …continued

GND = 0 V; CL = 50 pF; for test circuit see Figure 7.

Symbol Parameter

Conditions

25

C

40 C to +125 C Unit

Min

Typ

Max

Max

(85

C)

Max

(125

C)

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6.

Input to output propagation delays

Table 8.

Measurement points

Type

Input

Output

VM

VM

VX

VY

74HC00

0.5VCC

0.5VCC

0.1VCC

0.9VCC

74HCT00

1.3 V

1.3 V

0.1VCC

0.9VCC