74HC_HCT573

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 7 — 4 March 2016

5 of 20

NXP Semiconductors

74HC573; 74HCT573

Octal D-type transparent latch; 3-state

6.

Functional description

[1]

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;

Z = high-impedance OFF-state.

7.

Limiting values

[1]

For SO20: Ptot derates linearly with 8 mW/K above 70 C.

For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.

Table 3.

Function table[1]

Operating mode

Control

Input

Internal

latches

Output

OE

LE

Dn

Qn

Enable and read register (transparent

mode)

LH

L

LL

HH

H

Latch and read register

L

L

l

L

L

hH

H

Latch register and disable outputs

H

L

l

L

Z

hH

Z

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

0.5

+7

V

IIK

input clamping current

VI < 0.5 V or VI >VCC +0.5 V

-

20

mA

IOK

output clamping current

VO < 0.5 V or VO >VCC +0.5 V

-

20

mA

IO

output current

VO = 0.5 V to (VCC +0.5 V)

-

35

mA

ICC

supply current

-

+70

mA

IGND

ground current

70

-

mA

Tstg

storage temperature

65

+150

C

Ptot

total power dissipation

SO20, SSOP20, TSSOP20 and DHVQFN20

packages

[1]

-

500

mW