DS3177 datasheet(32/230 Pages) AD

32 / 230 page

DS3177 DS3/E3 Single-Chip Transceiver

32 of 230

PIN NAME

TYPE

PIN DESCRIPTION

TSOFO /

TDEN

Framer Start Of Frame / Data Enable

See Table 10-21.

TSOFO: When the port framer is configured for the DS3 or E3 framed modes and the

TSOFO pin function is selected, this signal is used to indicate the start of the DS3/E3

frame on the TSER pin. This signal pulses high three clocks before the first overhead

bit in a DS3 or E3 frame that will be input on TSER. The signal is updated on the

positive clock edge of the referenced clock pin if the clock pin signal is not inverted,

otherwise it is updated on the falling edge of the clock. The signal is typically

referenced to the TCLKI transmit clock input pins, but it can be referenced to the

TLCLK, TCLKO, RCLKO and RLCLK clock pins.

This signal can be inverted.

TDEN: When the port framer is configured for the DS3 or E3 framed modes and the

TDEN pin function is selected, this signal is used to mark the DS3/E3 frame bits on

the TSER pin. The signal goes high three clocks before the start of DS3/E3 payload

bits and goes low three clocks before the end of the DS3/E3 payload bits. The signal

is updated on the positive clock edge of the referenced clock pin if the clock pin signal

is not inverted, otherwise it is updated on the falling edge of the clock. The signal is

typically referenced to the TCLKI transmit clock input pins, but it can be referenced to

the TLCLK, TCLKO, RCLKO and RLCLK clock pins.

This signal can be inverted.

RSER

Receive Serial Data

RSER: When the port framer is configured for the DS3 or E3 framed modes, this pin

outputs the receive data signal from the LIU or receive line pins. The signal is updated

on the positive clock edge of the referenced clock pin if the clock pin signal is not

inverted, otherwise it is updated on the falling edge of the clock. The signal is typically

referenced to the RCLKO receive clock output pin, but it can be referenced to the

RGCLK and RLCLK clock pins.

This signal can be inverted

DS3: 44.736 Mbps +20ppm

E3: 34.368 Mbps +20ppm

RCLKO /

RGCLK

Receive Clock Output / Gapped Clock

See Table 10-24.

RCLKO: When the port framer is configured for the DS3 or E3 framed modes and

RCLKO is selected, this clock output signal is active. It is the same as the internal

receive framer clock. This clock is typically used for the reference clock for the RSER,

RSOFO / RDEN signals but can also be used as the reference for the RPOS / RDAT,

RNEG / RLCV, TSOFI, TSER, TSOFO / TDEN, TPOS / TDAT and TNEG signals.

This signal can be inverted.

DS3: 44.736 MHz +20 ppm

E3: 34.368 MHz +20 ppm

RGCLK: When the port is configured for DS3/E3 framed mode and RGCLK is

selected, this gated clock output signal is active. It is the same as the internal receive

framer clock gated by RDEN. This clock is typically used for the reference clock for

the RSER.

This signal can be inverted

RSOFO /

RDEN

Receive Framer Start Of Frame /Data Enable

See Table 10-23.

RSOFO: When the port framer is configured for the DS3 or E3 framed modes and the

RSOFO pin function is enabled, this signal is used to indicate the start of the DS3/E3

frame. This signal indicates the first DS3/E3 overhead bit on the RSER pin when high.

The signal is updated on the positive clock edge of the referenced clock pin if the

clock pin signal is not inverted, otherwise it is updated on the falling edge of the clock.

The signal is typically referenced to the RCLKO receive clock output pin, but it can be

referenced to the RLCLK clock input pin.

This signal can be inverted.

RDEN: When the port framer is configured for the DS3 or E3 framed modes and the

RDEN pin function is enabled, this signal is used to indicate the DS3/E3 payload bit

DS3177 Datasheet(PDF) 32 Page - Analog Devices

DS3177 Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL