Document No. 008-0284-0

Page 2 - 4

Rev. D

Model 635

7.5x5.0mm Low Cost

LVPECL or LVDS Clock Oscillator

ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Maximum Supply Voltage

-

-0.5

-

5.0

V

Storage Temperature

-

-55

-

125

°C

LVPECL and LVDS

19.44

-

250

Frequency Stability

(See Note 2 and Ordering Information)

--

-

20, 25, 50

or 100

± ppm

Operating Temperature

Commercial

-20

70

Industrial

-40

85

2.38

2.5

2.63

3.14

3.3

3.47

Supply Current

LVPECL

-

50

100

LVDS

-

25

60

Start Up Time

-3

5

ms

Phase Jitter

tjrms

Bandwidth 12 kHz - 20 MHz

-

-

1

ps RMS

Period Jitter

pjrms

-

-

-

5

ps RMS

Enable Function

Standby

Enable Input Voltage

Pin 1 or Pin 2 Logic '1', Output Enabled

--

V

Disable Input Voltage

Pin 1 or Pin 2 Logic '0', Output Disabled

-

-

Disable Current

Pin 1 or Pin 2 Logic '1' , Output Disabled

-

-

20

uA

Enable Time

Pin 1 or Pin 2 Logic '1'

--

5

ns

LVPECL WAVEFORM

Output Load

--

50

-

Ohms

Output Duty Cycle

SYM

45

-

55

%

Output Voltage Levels

Logic '1' Level

PECL Load

--

Logic '0' Level

PECL Load

-

-

Rise and Fall Time

-0.8

1.0

-0.5

0.6

LVDS WAVEFORM

Output Load

Between Outputs

-

100

-

Ohms

Output Duty Cycle

SYM

@ 1.25V

45

-

55

%

Differential Output Voltage

RL = 100 Ohms

247

350

454

mV

Differential Output Error

-

-

-

-

50

mV

Offset Voltage

LVDS Load

1.125

1.25

1.375

V

Offset Error

-

-

-

-

50

mV

Output Voltage Levels

Logic '1' Level

LVDS Load

-

1.43

1.6

Logic '0' Level

LVDS Load

0.9

1.1

-

Rise and Fall Time

-0.8

1.0

-0.5

0.6

Notes:

1.

2.

-MHz

-°C

25

@ 20% - 80% Levels

mA

V

V

For frequencies above 160 MHz consult factory for availability.

@ 20% - 80% Levels

ns

Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging.

± 5 %

Maximum Load

ns

Supply Voltage

V

PECL/LVDS OUTPUT WAVEFORM

Tr

Tf

UPTIME (t)

PERIOD (T)

80%

50%

20%

DUTY CYCLE = t/T x 100 (%)

OUT

OUT

OH

V

OL

V

ENABLE TRUTH TABLE

PIN 1 or PIN 2

PIN 4 / PIN 5

Logic ‘1’

Output

Open

Output

Logic ‘0’

High Imp.