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ST10F269-Q3 Datasheet(PDF) 47 Page - STMicroelectronics |
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ST10F269-Q3 Datasheet(HTML) 47 Page - STMicroelectronics |
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47 / 160 page  ST10F269 47/160 xxIC (yyyyh / zzh) SFR Area Reset Value: - - 00h 8.4 - Exception and Error Traps List Table 8 shows all of the possible exceptions or error conditions that can arise during run-time : * - All the class B traps have the same trap number (and vector) and the same lower priority compare to the class A traps and to the resets. - Each class A traps has a dedicated trap number (and vector). They are prioritized in the second priority level. - The resets have the highest priority level and the same trap number. - The PSW.ILVL CPU priority is forced to the highest level (15) when these exeptions are serviced. 15 14 13 12 11 10 9876543210 -------- xxIR xxIE ILVL GLVL RW RW RW RW Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests. Fh: Highest priority level 0h: Lowest priority level xxIE Interrupt Enable Control Bit (individually enables/disables a specific source) ‘0’: Interrupt Request is disabled ‘1’: Interrupt Request is enabled xxIR Interrupt Request Flag ‘0’: No request pending ‘1’: This source has raised an interrupt request Table 8 : Trap Priorities Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap* Priority Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow RESET RESET RESET 00’0000h 00’0000h 00’0000h 00h 00h 00h III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008h 00’0010h 00’0018h 02h 04h 06h II II II Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028h 00’0028h 00’0028h 00’0028h 00’0028h 0Ah 0Ah 0Ah 0Ah 0Ah I I I I I Reserved [002Ch - 003Ch] [0Bh - 0Fh] Software Traps TRAP Instruction Any 0000h – 01FCh in steps of 4h Any [00h - 7Fh] Current CPU Priority |
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