MIC2591B datasheet(21/34 Pages) MICREL

21 / 34 page

MIC2591B

Micrel

March 2005

M9999-033105

of the fault conditions listed above and deasserted when

one or all STAT[A/B] Register Bits D[4], D[2], D[0] and/or CS

SMBus “echo reset” WRITE_BYTE cycle. For polled-mode

operation,theINTMSKbitshouldbesettoLogical“1,”thereby

inhibiting /INT output pin operation.

ForthoseSMI-controlapplicationswherethe/FORCE_ON[A/B]

inputsareneededfordiagnosticpurposes,the/FORCE_ON[A/B]

inputs must be enabled; that is, CNTRL[A/B] Register Bit

D[2] should read Logical “0.” Once /FORCE_ON[A/B] inputs

are asserted, all output voltages are present with all circuit

protection features disabled, including overtemperature pro-

tection on VAUX[A/B] outputs. To inhibit /FORCE_ON[A/B]

operation, a Logical “1” shall be written to the CNTRL[A/B]

HPI-only Control Applications

In applications where the MIC2591B is controlled only by the

HPI, SMBus signals SCL, SDA, and /INT signals are con-

nected to VSTBY as shown in Figure 6. In this conﬁguration,

STBY

the MIC2591B’s /FAULT[A/B] outputs are activated after

power-on-reset and become asserted when:

EitherorbothexternalON[A/B]andAUXEN[A/B]inputsignals

are asserted, AND

• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-

age is lower than its respective ULVO threshold,

• The fast OC circuit breaker[A/B] has tripped, OR

• The slow OC circuit breaker[A/B] has tripped AND

its ﬁlter timeout[A/B] has expired, OR

• The slow OC circuit breaker[A/B] has tripped AND

Slot[A/B] die temperature > 140°C, OR

• The MIC2591B’s global die temperature > 160°C

In order to clear /FAULT[A/B] outputs once asserted, either

or both ON[A/B] and AUXEN[A/B] input signals must be

deasserted. Please see /FAULT[A/B] pin description for ad-

ditional information.

If the /FORCE_ON[A/B] inputs are used for diagnostic pur-

poses, both /FAULT[A/B] and /PWRGD[A/B] outputs are

deasserted once /FORCE_ON[A/B] inputs are asserted.

Serial Port Operation

The MIC2591B uses standard SMBus Write_Byte and

Read_Byte operations for communication with its host. The

SMBus Write_Byte operation involves sending the device’s

/INT*

/FAULT_[A/B]

I3VOUT[A/B]

3VOUT[A/B]

IAUX_OUT[A/B]

VAUX_OUT[A/B]

AUXEN[A/B]

LIM(3V)

STEADY-STATE

ON[A/B]

+3.3V

tPOR

VSTBY

UVLO

tFLT

LIM(AUX)

STEADY-STATE

* /INT de-asserted by software

12VOUT[A/B]

/PWRGD_[A/B]

Figure 9. Hot-Plug Interface Operation

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