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ST20-C1 Datasheet(PDF) 76 Page - STMicroelectronics |
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ST20-C1 Datasheet(HTML) 76 Page - STMicroelectronics |
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76 / 205 page ![]() 6.7 Traps 76/205 ® 6.7 Traps The ST20-C1 has a system of traps which act as software generated interrupts. Any level of exception can be called as a user exception using ecall. This mechanism can be used for system calls to an operating system. In addition some special exception levels are reserved for system use to provide for the trapping of breakpoints, scheduling events, illegal operations and the machine becoming idle. The reserved ‘system’ exception levels are described in section 6.1. If a system trap event occurs or a trap is called at an exception level which has a null trap handler then the CPU ignores the trap and continues. When a non-null trap handler is started, the trap_mode bit of the status register is set and the user_mode bit is cleared. The interrupt_mode bit is not altered. The trap_mode bit indicates that a trap handler is currently executing, so it is cleared if the trap handler is interrupted. 6.8 Setting up the exception handler To create an exception handler, an exception work space area must be created, with enough space for the exception handler’s stack and 8 words at the top of the work space for the exception control block, as defined in Table 6.3. For minimum interrupt latency, interrupt handler control blocks should be in fast memory, preferably on-chip. The normal work space and control block of an exception handler is shown in Figure 6.2. In the control block, ex.HandlerIptr must be initialized to point to the entry point of the exception handler code. Figure 6.2 Exception handler ex.HandlerIptr Pointer OR 1 Exception handler code entry point Interrupted or trapped state Work space Exception vector table Exception level (7 words) (word offset) ExceptionBase Exception Handler Initial exception handler Wptr |
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