ST62T35B datasheet(59/82 Pages) STMICROELECTRONICS

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ST62T35B/E35B

4.6 SERIAL PERIPHERAL INTERFACE (SPI)

The on-chip SPI is an optimized serial synchro-

nous interface that supports a wide range of in-

dustry standard SPI specifications. The on-chip

SPI is controlled by small and simple user soft-

ware to perform serial data exchange. The serial

shift clock can be implemented either by software

(using the bit-set and bit-reset instructions), with

the on-chip Timer 1 by externally connecting the

SPI clock pin to the timer pin or by directly apply-

ing an external clock to the Scl line.

The peripheral is composed by an 8-bit Data/shift

pin is the serial shift input and Sout is the serial

shift output. These two lines can be tied together

to implement two wires protocols (I C-bus, etc).

When data is serialized, the MSB is the first bit.

Sin has to be programmed as input. For serial out-

put operation Sout has to be programmed as

open-drain output.

The SCL, Sin and Sout SPI clock and data signals

are connected to 3 I/O lines on the same external

pins. With these 3 lines, the SPI can operate in the

following operating modes: Software SPI, S-BUS,

I C-bus and as a standard serial I/O (clock, data,

enable). An interrupt request can be generated af-

ter eight clock pulses. Figure 35. shows the SPI

block diagram.

The SCL line clocks, on the falling edge, the shift

slave mode, the SCL pin must be programmed as

input and an external clock must be supplied to

this pin to drive the SPI peripheral.

In master mode, SCL is programmed as output, a

clock signal must be generated by software to set

and reset the port line.

Figure 35. SPI Block Diagram

Set Res

CLK

RESET

4-Bit Counter

(Q4=High after Clock8)

Data Reg

Direction

I/O Port

8-Bit Data

Shift Register

Reset

Load

DOUT

Output

Enable

8-Bit Tristate Data I/O

RESET

I/O Port

DIN

D0............... .............D7

to Processor Data Bus

OPR Reg.

DIN

SCL

Sin

Sout

SPI Interrupt Disable Register

SPI Data Register

Data Reg

Direction

Data Reg

Direction

DOUT

Write

Read

Interrupt

VR01504

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