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ST72589BW Datasheet(PDF) 21 Page - STMicroelectronics |
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ST72589BW Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 158 page ![]() ST72589BW, ST72389BW 21/158 MAIN CLOCK CONTROLLER (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) See description in MISCELLANEOUS Register Section. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read /Write Reset Value: 0000 0000 (00h) Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details. Bit 2:1 = CP1-CP0 CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software Bit 4 = Reserved, always read as 0. Bit 3:2 = TB1-TB0 Time base control These bits select the programmable divider time base. They are set and cleared by software. A modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disable 1: Oscillator interrupt enable This interrupt allows to exit from ACTIVE-HALT mode. When this bit is set, calling the ST7 soft- ware HALT instruction accesses the ACTIVE- HALT power saving mode. Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has measured the selected elapsed time (TB1:0). 0: timeout not reached 1: timeout reached Warning: BRES and BSET instructions must not be used on the MCCSR register to avoid unwant- ed clearing of OIF bit. 70 SMS CP1 CP0 0 TB1 TB0 OIE OIF fCPU in SLOW mode CP1 CP0 fOSC / 4 0 0 fOSC / 8 0 1 fOSC / 16 1 0 fOSC / 32 1 1 Counter Prescaler Time Base TB1 TB0 fOSC=8MHz fOSC=16MHz 32000 4ms 2ms 0 0 64000 8ms 4ms 0 1 160000 20ms 10ms 1 0 400000 50ms 25ms 1 1 |
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