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ADS7229 Datasheet(PDF) 33 Page - Texas Instruments

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Part # ADS7229
Description  LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
PDF  46 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS7229 Datasheet(HTML) 33 Page - Texas Instruments

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ADS7229
#1
SDI
SDO
ADS7229
#2
SDI
SDO
ADS7229
#3
SDI
SDO
MicroController
SDI
SDO
GPIO1
GPIO2
GPIO3
Programdevice#1CFR_D[7:5]=XX0b
INT
CS
CONVST
CS
CONVST
CS
CONVST
EOC/INT
CDI
CDI
Programdevice#2and#3CFR_D[7:5]=XX1b
SCLK
SCLK
SCLK
SCLK
READResult
EOC#1
(activelow)
Common CONVST
F /
#
S
1
CS
INT
(activelow)
Common SCLK
CascadedManualTr
Samplin
igger/ReadWhile
g
(UseinternalCCLK,EOC,and
programmedasactivelow)
heldlowduringtheNtimes16bitstransfercycle
INT
CS
SDO#2
SDI
t
CONV =18CCLKs
1……………………16
1101b
READResult
1……………………16
Nth
1……………………16
1101b
READResult
FS/
#2
CS
FS/
#3
CS
SDO#1
Nthfrom #1
SDO#3
Nthfrom #2
Nthfrom #3
Nthfrom #1
Nthfrom #1
Nthfrom #2
t
4
t
4
1101b
t
SAMPLE1 =3CCLKsMin
ADS7229
ADS7230
www.ti.com........................................................................................................................................................................................................ SBAS437 – MAY 2008
Figure 61. Multiple Converters Connected Using Chain Mode
When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while
the other converters are configured in chain mode. When a converter is configured in chain mode, the CDI input
data go straight to the output register; therefore, the serial input data passes through the converter with a 16
SCLK delay (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. Figure 62 shows a
detailed timing diagram. In this timing, the conversions in each device are performed simultaneously.
Figure 62. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS
Care must be given to handle the multiple CS signals when the converters operate in daisy-chain mode. The
different chip select signals must be low for the entire data transfer (in this example, 48 bits for three converters).
The first 16-bit word after the falling chip select is always the data from the chip that received the chip select
signal.
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS7229 ADS7230



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