BLOCK DIAGRAM

2:1

MUX

PRBS

Generator

10Bit

Registers

TD(0−9)

PRBSEN

LOOPEN

Parallelto

Serial

PhaseGenerator

Clock

REFCLK

Control

Logic

ENABLE

TESTEN

Interpolator

and

ClockExtraction

PRBS

Verification

SerialtoParallel

and

CommaDetect

Clock

RBC1

RBC0

SYNC/PASS

RD(0−9)

SYNCEN

RBCMODE

JTAG

Control

Register

JTMS

JTRSTN

JTDI

TCK

JTDO

2:1

MUX

2:1

MUX

Clock

Data

TXP

TXN

RXP

RXN

LOS

TLK2211

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

SIGNAL

Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper

TXP

62

PECL

or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high

TXN

61

O

and are active when LOOPEN is low.

RXP

54

PECL

Differential input receive. RXP and RXN together are the differential serial input interface from a

copper or an optical I/F module.

RXN

52

I

Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter

interface (100 MHz to 160 MHz). The transmitter uses this clock to register the input data

REFCLK

22

I

(TD0-TD9) for serialization.

The data (TDx) is registered on the rising edge of REFCLK.

Transmit data. During normal operation these inputs carry 10-bit parallel data output from a

2–4, 6–9,

protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is

TD0–TD9

I

11–13

clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with

TD0 sent as the first bit.

45, 44, 43,

Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol

41, 40, 39,

layer. The data is referenced to terminals RBC0 and RBC1, depending on the receive clock mode

RD0–RD9

O

38, 36, 35,

selected. RD0 is the first bit received.

34

Copyright © 2008, Texas Instruments Incorporated

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