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ADS62P43 Datasheet(PDF) 39 Page - Texas Instruments |
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ADS62P43 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 70 page ![]() www.ti.com fS − Sampling Frequency − MSPS 0 10 20 30 40 50 60 0 25 50 75 100 125 G079 1.8 V, 5 pF 3.3 V, 5 pF 3.3 V, 10 pF 3.3 V, No Load 1.8 V, No Load 1.8 V, 10 pF ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561A – JULY 2007 – REVISED FEBRUARY 2008 COMMON PLOTS (continued) All plots are at 25 °C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 V PP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted) DRVDD current (CMOS) vs SAMPLING FREQUENCY across load capacitance at 2 MHz input frequency Figure 79. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 |
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