AD5024 datasheet(19/28 Pages) AD

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AD5024/AD5044/AD5064

Rev. 0 | Page 19 of 28

INPUT SHIFT REGISTER

The AD5024/AD5044/AD5064 input shift register is 32 bits wide.

The first four bits are don’t cares. The next four bits are the com-

mand bits, C3 to C0 (see Table 7), followed by the 4-bit DAC

address bits, A3 to A0 (see Table 8), and finally the bit data-word.

The data-word comprises 12-, 14-, or 16-bit input code followed

by 8, 6, or 4 don’t care bits for the AD5024/AD5044/AD5064

(see Figure 43, Figure 44, and Figure 45). These data bits are

transferred to the DAC register on the 32nd falling edge of SCLK.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 32 falling edges of SCLK, and the DAC is updated on the

32nd falling edge. However, if SYNC is brought high before the

32nd falling edge, this acts as an interrupt to the write sequence.

The shift register is reset, and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see

Figure 46

ADDRESS BITS

COMMAND BITS

D11 D10

XXXX

DB31 (MSB)

DB0 (LSB)

DATA BITS

Figure 43. AD5024 Input Register Content

ADDRESS BITS

COMMAND BITS

D13 D12 D11 D10

DB31 (MSB)

DB0 (LSB)

DATA BITS

Figure 44. AD5044 Input Register Content

ADDRESS BITS

COMMAND BITS

D15 D14 D13 D12 D11 D10

DB31 (MSB)

DB0 (LSB)

DATA BITS

Figure 45. AD5064 Input Register Content

SCLK

DIN

DB31

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 32ND FALLING EDGE

DB31

DB0

SYNC

Figure 46. SYNC Interrupt Facility

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