AD5024 datasheet(21/28 Pages) AD

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AD5024/AD5044/AD5064

Rev. 0 | Page 21 of 28

CLEAR CODE REGISTER

The AD5024/AD5044/AD5064 have a hardware CLR pin that

is an asynchronous clear input. The CLR input is falling edge

sensitive. Bringing the CLR line low clears the contents of the

input register and the DAC registers to the data contained in

the user-configurable CLR register and sets the analog outputs

accordingly (see

). This function can be used in system

calibration to load zero scale, midscale, or full scale to all channels

together. Note that zero scale and full scale are outside the linear

region of the DAC. These clear code values are user-programmable

by setting two bits, Bit DB1 and Bit DB0, in the control register

(see

). The default setting clears the outputs to 0 V.

Command 0101 is designated for loading the clear code register

(see

Table 11

Table 7

The part exits clear code mode on the 32nd falling edge of the

next write to the part. If CLR is activated during a write

sequence, the write is aborted.

The CLR pulse activation time, which is the falling edge of CLR

to when the output starts to change, is typically 10.6 μs. If outside

the DAC linear region, it typically takes 10.6 μs after executing

CLR for the output to start changing (see

Figure 33

See Table 12 for contents of the input shift register during the

loading clear code register operation.

LDAC FUNCTION

Hardware LDAC Pin

The outputs of all DACs can be updated simultaneously using

the hardware LDAC pin, as shown in

Figure 2

Synchronous LDAC: After new data is read, the DAC registers

are updated on the falling edge of the 32nd SCLK pulse. LDAC

can be permanently low or pulsed.

Asynchronous LDAC: The outputs are not updated at the same

time that the input registers are written to. When LDAC goes

low, the DAC registers are updated with the contents of the

input register.

Software LDAC Function

Alternatively, the outputs of all DACs can be updated simulta-

neously using the software LDAC function by writing to Input

reserved for this software LDAC function.

The LDAC register gives the user extra flexibility and control

over the hardware LDAC pin (see

). Setting the

Table 14

LDAC

bit register (DB0 to DB3) to 0 for a DAC channel means that

this channel’s update is controlled by the hardware LDAC pin.

If this bit is set to 1, this channel updates synchronously; that is,

the DAC register is updated after new data is read, regardless of

the state of the hardware LDAC pin.

It effectively sees the hardware LDAC pin as being tied low.

(See

for the

Table 13

LDAC register mode of operation.) This

flexibility is useful in applications where the user wants to simul-

taneously update select channels while the rest of the channels

are synchronously updating.

Writing to the DAC using Command 0110 loads the 4-bit

LDAC register (DB3 to DB0). The default for each channel is 0;

that is, the LDAC pin works normally. Setting the bits to 1 means

that the DAC channel is updated regardless of the state of the

LDAC pin.

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the board.

The printed circuit board containing the AD5024/AD5044/

AD5064 should have separate analog and digital sections. If the

AD5024/AD5044/AD5064 is in a system where other devices

require an AGND-to-DGND connection, the connection should

be made at one point only. This ground point should be as close

as possible to the AD5024/AD5044/AD5064.

The power supply to the AD5024/AD5044/AD5064 should

be bypassed with 10 μF and 0.1 μF capacitors. The capacitors

should physically be as close as possible to the device, with the

0.1 μF capacitor ideally right up against the device. The 10 μF

capacitors are the tantalum bead type. It is important that the

0.1 μF capacitor have low effective series resistance (ESR) and

low effective series inductance (ESI), such as is typical of common

ceramic types of capacitors. This 0.1 μF capacitor provides a low

impedance path to ground for high frequencies caused by

transient currents due to internal logic switching.

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Clocks and other fast switching digital signals should

be shielded from other parts of the board by digital ground. Avoid

crossover of digital and analog signals, if possible. When traces

cross on opposite sides of the board, ensure that they run at right

angles to each other to reduce feedthrough effects through the

board. The best board layout technique is the microstrip tech-

nique, where the component side of the board is dedicated to the

ground plane only and the signal traces are placed on the solder

side. However, this is not always possible with a 2-layer board.

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