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AT89S8253-24JC Datasheet(PDF) 13 Page - ATMEL Corporation

Part # AT89S8253-24JC
Description  8-bit Microcontroller with 12K Bytes Flash and 2K Bytes EEPROM
PDF  56 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT89S8253-24JC Datasheet(HTML) 13 Page - ATMEL Corporation

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AT89S8253 [Preliminary]
3286A–MICRO–7/04
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S8253 operate the same way as Timer 0 and Timer 1 in the
AT89S51 and AT89S52. For more detailed information on the Timers’ operation, refer to the
Atmel Web site (www.atmel.com). From the home page, select “Products,” then “Microcontrol-
lers”, then “8051-Architecture”, then “Documentation”, and “Other Documents”. Open the
Adobe Acrobat file “AT89 Series Hardware Description.”
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON (see Table 8 on page 14). Timer 2
has three operating modes: capture, auto-reload (up or down counting), and baud rate gener-
ator. The modes are selected by bits in T2CON, as shown in Table 8.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is
incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the
count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its cor-
responding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle,
the count is incremented. The new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected. Since two machine cycles
(24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it
changes, the level should be held for at least one full machine cycle.
Table 7. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
MODE
0
0
1
16-bit Auto-reload
0
1
1
16-bit Capture
1
X
1
Baud Rate Generator
X
X
0
(Off)



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