AT89S8253-24JC datasheet(4/56 Pages) ATMEL

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AT89S8253 [Preliminary]

3286A–MICRO–7/04

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source six TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the

weak internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally

being pulled low will source current (I

IL,150 µA typical) because of the weak internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and

during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2

Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash

programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source six TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the

weak internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally

being pulled low will source current (I

IL,150 µA typical) because of the weak internal pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S8253, as shown in the

following table.

Note:

1. All pins in ports 1 and 2 and almost all pins in port 3 (the exceptions are P3.2 INT0 and P3.3

INT1) have their weak internal pull-ups disabled in the Power-down mode. Port pins P3.2

(INT0) and P3.1 (INT1) are active even in Power-down mode (to be able to sense an

interrupt request to exit the Power-down mode) and as such still have their weak internal

pull-ups turned on.

RST

Reset input. A high on this pin for at least two machine cycles while the oscillator is running

resets the device.

ALE/PROG

Address Latch Enable. ALE/PROG is an output pulse for latching the low byte of the address

(on its falling edge) during accesses to external memory. This pin is also the program pulse

input (PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may

be used for external timing or clocking purposes. Note, however, that one ALE pulse is

skipped during each access to external data memory.

Port Pin

Alternate Functions

P3.0

RXD (serial input port)

P3.1

TXD (serial output port)

P3.2

INT0 (external interrupt 0)(1)

P3.3

INT1 (external interrupt 1)(1)

P3.4

T0 (timer 0 external input)

P3.5

T1 (timer 1 external input)

P3.6

WR (external data memory write strobe)

P3.7

RD (external data memory read strobe)

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