LM3S328 Data Sheet
October 8, 2006
39
Preliminary
5.1
Block Diagram
Figure 5-1.
JTAG Module Block Diagram
5.2
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1. The JTAG module is
composed of the Test Access Port (TAP) controller and serial shift chains with parallel update
registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS
inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines
when the serial shift chains capture new data, shift data from TDI towards TDO, and update the
parallel load registers. The current state of the TAP controller also determines whether the
Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register
(IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel
load register determines which DR chain is captured, shifted, or updated during the sequencing of
the TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 44 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 348 for JTAG timing diagrams.
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TRST
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
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