C504 datasheet(39/225 Pages) SIEMENS

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External Bus Interface

C504

Semiconductor Group

4-8

1997-10-01

Between two ALE pulses the data at port 0 is latched (at 6

CLCL after ALE rising edge) and compared

internally with the ROM/OTP content of the actual address. If an verify error is detected, the error

condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of

the last 16 verify operations is output at P3.5. P3.5 is always set or cleared after each 16 byte block

of the verify sequence. In ROM/OTP verification mode 2, the C504 must be provided with a system

clock at the XTAL pins.

Figure 4-5 shows an application example of a external circuitry which allows to verify a protected

ROM/OTP inside the C504 in ROM/OTP verification mode 2. With RESET going inactive, the C504

starts the ROM/OTP verify sequence. Its ALE is clocking an 14-bit address counter. This counter

generates the addresses for an external EPROM which is programmed with the content of the

internal (protected) ROM/OTP. The verify detect logic typically displays the state of the verify error

output P3.5. P3.5 can be latched with the falling edge of ALE.

When the last byte of the internal ROM/OTP has been handled, the C504 starts generating a PSEN

signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end

of the internal ROM/OTP verification.

Figure 4-5

ROM/OTP Verification Mode 2 - External Circuitry Example

MCB02595

Verify

Detect

Logic

14-Bit

Address

Counter

Ω

Compare

Code

ROM

P3.5

ALE

RESET

Port

C504-2R

P2.7

PSEN

CLK

- A13

C504-2E

C504 Datasheet(PDF) 39 Page - Siemens Semiconductor Group

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