C504 datasheet(13/225 Pages) SIEMENS

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Introduction

C504

Semiconductor Group

1-6

1997-10-01

P3.0-P3.7

5, 7-13

I/O

Port 3

is an 8-bit bidirectional port. P3.0 (R

×D) and P3.1 (T×D)

operate as defined for the C501. P3.2 to P3.7 contain the

external interrupt inputs, timer inputs, input and as an

additional optinal function four of the analog inputs of the

A/D-converter. Port 3 pins are assigned to be used as

analog inputs by the bits of SFR P3ANA.

P3.6/WR can be assigned as a third interrupt input. The

functions are assigned to the pins of port 3 as follows:

P3.0 / RxD

Receiver data input (asynch.) or data

input/output (synch.) of serial

interface

P3.1 / TxD

Transmitter data output (asynch.) or

clock output (synch.) of serial

interface

P3.2 / AN4 / INT0

Analog input channel 4 / external

interrupt 0 input / timer 0 gate control

input

P3.3 / AN5 / INT1

Analog input channel 5 / external

interrupt 1 input / timer 1 gate control

input

P3.4 / AN6 / T0

Analog input channel 6 / timer 0

counter input

P3.5 / AN7 / T1

Analog input channel 7 / timer 1

counter input

P3.6 / WR / INT2

WR control output; latches the data

byte from port 0 into the external data

memory /

external interrupt 2 input

P3.7 / RD

RD control output; enables the

external data memory

CTRAP

CCU Trap Input

With CTRAP = low the compare outputs of the CAPCOM

unit are switched to the logic level as defined in the COINI

CTRAP is an input pin with an internal pullup resistor. For

power saving reasons, the signal source which drives the

CTRAP input should be at high or floating level during

power-down mode.

I = Input

O = Output

Table 1-1

Pin Definitions and Functions (cont’d)

Symbol

Pin Number

(P-MQFP-44)

I/O

Function

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