STLC1502 datasheet(19/81 Pages) STMICROELECTRONICS

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STLC1502

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Defines the data width of the external memory device:

•

00 - Byte (8 bit)

•

01 - Half Word (16 bit)

•

10 - Word (32 bit)

DATALAT: Data Latency

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Defines the number of memory clock cycles between the start of a memory read access and the first

valid data.

•

The DATALAT value is valid between 0 and 3.

SETUPTIME: Setup Time

•

Defines the number of memory clock cycles the memory driver spends in the DECODE state before

accessing the external memory.

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The SETUPTIME value is valid between 0 and 7.

IDLETIME: Idle Time

•

Defines the minimum time the memory driver must spend in the IDLE state following memory

accesses.

•

The value defines the number of Memory Clock cycles.

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The IDLETIME value is valid between 0 and 7.

SDRAMCOL: SDRAM Column Width Definition

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Specifies the width of the SDRAM column address:

•

00 - 8 bits

•

01 - 9 bits

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10 - 10 bits

•

11 - reserved

6.3.1.2 SDRAM Configuration registers

These registers are write only. A write access to the high registers will start the SDRAM configuration cycle,

during which the value written to the register will be asserted on the memory bus for a one clock period.

Low SDRAM Configuration Registers

MIAB: Memory Interface Address Bus

High SDRAM Configuration Registers

98765

43210

Reserved

MIAB

Reserved

MIVE

MIAA

MISA

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