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STLC1502 Datasheet(PDF) 20 Page - STMicroelectronics |
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STLC1502 Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 81 page  STLC1502 20/81 MIAB: Memory Interface Address Bus MIWE: Memory Interface Write Enable MIAA: Memory Interface Access Active (nCAS) MISA: Memory Interface Setup Active (nRAS) After the power-up the CPU must configure each SDRAM device, i.e. perform precharge-refresh-mode register set procedure. 6.3.1.3 Memory Configuration register Memory configuration registers are used to setup parameters that are same for all banks: PWS: Power save mode • If PWS bit is set to’1’, the next refresh cycle will set the memory devices in the self-refresh mode. • The memories will exit the self-refresh mode, when the PWS mode is set to’0’. TYPE: Memory type: • The TYPE bit is used to select a type of the external memory. •1 - SDRAM •0 - EDO B3EN: Bank 3 enable B2EN: Bank 2 enable B1EN: Bank 1 enable B0EN: Bank 0 enable • The bank enable bits are used to enable each bank separately. • If an AHB transfer is accessing a disabled bank, the DRAM Controller will return the error response to the AHB master. REFR: Refresh period • The REFR value is used to determine the refresh period. The period can be set in the 1 us steps. • REFR Refresh Period • 00000000 Refresh is disabled • 00000001 Refresh period is 1us • 00000010 Refresh period is 2us •. • 11111111 Refresh period is 255us 6.4 DMA Controller • The DMA controller is intended to be used with the Ethernet switch block to transfer Ethernet frames between the Ethernet switch buffers and memory. • The DMAC needs initialization before starting operation. During operation it does not need interven- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PWS TYPE B3EN B2EN B1EN B0EN REFR |
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