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STLC5464 Datasheet(PDF) 3 Page - STMicroelectronics

Part # STLC5464
Description  MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED
PDF  83 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5464 Datasheet(HTML) 3 Page - STMicroelectronics

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III.5
MEMORY INTERFACE . . . . ...... ... . . . . . . .... .. . . . . ..... ..... ..... .... .
31
III.5.1
Function Description . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
31
III.5.2
Choice of memory versus microprocessor and capacity required . . . . . . .... ..... . .
31
III.5.3
Memory Cycle . .... . . . ... ..... ...... .. . . ... . . .... . . .. . . .... . . ... .. . . ..
31
III.5.4
SRAM interface . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .
32
III.5.4.1
18K x n SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... ..... . . . . .. ... . . .... ..
32
III.5.4.2
512K x n SRAM . .... . . . ... ..... ...... .. .. . . . . . .... . . .. . . .... . . ... .. .
32
III.5.5
DRAM Interface . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .
32
III.5.5.1
256K x n DRAM . .... . . . ... ..... ...... .. .. . . . . . .... . . .. . . .... . . ... .. .
32
III.5.5.2
1M x n DRAM . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .
33
III.5.5.3
4M x n DRAM . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .
33
III.6
BUS ARBITRATION . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
33
III.7
CLOCK SELECTION AND TIME SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . .
34
III.7.1
Clock Distribution Selection and Supervision . . . . . . . . . . . . . . . . . . . . . . . .... ..... .
34
III.7.2
VCXO Frequency Synchronization . .... . . . ... . . .. . . .. . . .... . . .. . . .... . . .. . .
34
III.8
INTERRUPT CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . .... ..... ..... . . . . .. ..
35
III.8.1
Description . .... . . . ... ..... ...... .. . . .... ..... . . .. . . .... . . ... .. . . .. ...
35
III.8.2
Operating Interrupts (INT0 Pin) . . . . ...... ... ..... . . ... .. . . . . ..... ..... ....
35
III.8.3
Time Base Interrupts (INT1 Pin) . . . . . . . . . . . . .... . . ... . . .... ..... ..... . . . . .
35
III.8.4
Emergency Interrupts (WDO Pin) . . ...... ..... .... ..... ..... . . . . . ..... .....
35
III.8.5
Interrupt Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... ..... . . . . .. ... . . .... ..
35
III.9
WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . .... .... ..... . . . . .. ... . . .... .. . . .
36
III.10
RESET . . . . . . ..... .... . . .... .... . ... .. .. . . . .... .. . . . . .... . . ... .. . . . . .
36
IV
DC SPECIFICATIONS . .... . . . ... ..... ..... .... . . .. . . .... . . .. . . .... . . ...
37
V
CLOCK TIMING . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .
38
V.1
SYNCHRONIZATION SIGNALS DELIVERED BY THE SYSTEM . . . . . . .... ..... . .
38
V.2
TDM SYNCHRONIZATION . . . . ...... ... . . . . . . . ... .. . . . . ..... ..... ..... ..
39
V.3
GCI INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... ..... . . . . .. ... . . .... ..
40
V.4
V* INTERFACE . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .
41
VI
MEMORY TIMING . .... . . . ... ..... ...... .. .. . . . . . .... . . .. . . .... . . ... .. .
42
VI.1
DYNAMIC MEMORIES . . . . ...... ... . . . . . . .... .. . . . . ..... ..... ..... .... .
42
VI.2
STATIC MEMORIEs . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
44
VII
MICROPROCESSOR TIMING . .... . . . ... .... . . .. . . .... . . .. . . .... . . .. . . ...
46
VII.1
ST9 FAMILY MOD0=1, MOD1=0, MOD2=0 . . . . . . . . . . . . . . . . . . . . . . . .... ..... .
46
VII.2
80C188 MOD0=1, MOD1=1, MOD2=0 . . . . .... ...... .... . . ... .. . . . . ..... ...
48
VII.3
80C186 MOD0=1, MOD1=1, MOD2=1 . . . . .... ...... .... . . ... .. . . . . ..... ...
50
VII.4
68000 MOD0=0, MOD1=0, MOD2=1 . . . . . . . . . . . . . . . . . . . . . . . .... ..... ..... . .
52
VII.5
TOKEN RING TIMING . .... . . . ... ..... ..... .... . . .. . . .... . . .. . . .... . . ...
54
VII.6
MASTER CLOCK TIMING . .... . . . ... ..... ... . . .... . . .. . . .... . . .. . . .... . .
54
CONTENTS (continued)
Page
STLC5464
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