M48Z32V datasheet(7/19 Pages) STMICROELECTRONICS

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M48Z32V

Operating modes

7/19

Operating modes

The M48Z32V also has its own Power-fail Detect circuit. The control circuitry constantly

monitors the single power supply for an out of tolerance condition. When VCC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

midst of unpredictable system operation brought on by low VCC. As VCC falls below

approximately VSO, the control circuitry connects the battery which maintains data until valid

power returns.

Table 2.

Operating modes

Note:

X = VIH or VIL; VSO = Battery back-up switchover voltage.

2.1

Read mode

The M48Z32V is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)

is low. The device architecture allows ripple-through access of data from eight of 262,144

locations in the static storage array. Thus, the unique address specified by the 15 Address

Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be

available at the Data I/O pins within Address Access time (tAVQV) after the last address input

signal is stable, providing that the E and G access times are also satisfied. If the E and G

access times are not met, valid data will be available after the latter of the Chip Enable

Access time (tELQV) or Output Enable Access time (tGLQV).

The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are

activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If

the Address Inputs are changed while E and G remain active, output data will remain valid

for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.

Mode

VCC

DQ0-DQ7

Power

Deselect

3.0 to 3.6V

VIH

High Z

Standby

WRITE

VIL

XVIL

DIN

Active

READ

VIL

VIH

DOUT

Active

READ

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

(1)

See Table 12 on page 15 for details.

High Z

CMOS standby

Deselect

≤ VSO(1)

High Z

Battery back-up

mode

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