TDA7502 datasheet(14/25 Pages) STMICROELECTRONICS

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SPI interfaces

TDA7502

14/25

Figure 10.

Debug port serial clock timing.

Figure 11.

Debug port acknowledge timing.

Table 13.

Debug port interface

No.

Characteristics

dclk = 40MHz

Unit

Min.

Max.

DBCK rise time

DBCK fall time

DBCK low

DBCK high

DBCK cycle time

200

DBRQN asserted to DBOUT (ACK) asserted

5 TDSP

DBCK high to DBOUT valid

DBCK high to DBOUT invalid

DBIN valid to DBCK low (set-up)

DBCK low to DBIN invalid (hold)

DBOUT (ACK) asserted to first DBCK high

2 Tc

DBOUT (ACK) assertion width

4.5 TDSP - 3

5 TDSP + 7

Last DBCK low of read register to first DBCK high

of next command

7 TDSP + 10

Last DBCK low to DBOUT invalid (Hold)

DBSEL setup to DBCK

TDSP

(1)

(3)

(4)

(5)

(2)

DBCK

(input)

D02AU1363

(6)

DBRQN

(input)

DBOUT

(output)

D02AU1364

(ACK)

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