M48Z129Y*, M48Z129V

6/16

READ Mode

The M48Z129Y/V is in the READ Mode whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The unique address specified by the 17 ad-

dress inputs defines which one of the 131,072

bytes of data is to be accessed. Valid data will be

dress Access Time) after the last address input

signal is stable, providing the E and G access

times are also satisfied. If the E and G access

times are not met, valid data will be available after

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

puts are changed while E and G remain active,

Data Hold Time) but will go indeterminate until the

next Address Access.

Figure 5. Address Controlled, READ Mode AC Waveforms

Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.

Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms

AI02324

tAVAV

tAVQV

tAXQX

DATA VALID

A0-A16

DQ0-DQ7

VALID

DATA VALID

AI01197

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A16

E

G

DQ0-DQ7

VALID