ORSPI4 datasheet(142/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

142

A programmable FIFO empty ﬂag (MC_RDFIFO_EMPTY) is available to the FPGA for the data FIFO. The FIFO

ﬂag threshold is set by the 4-bit software register ﬁeld MC_EMPTY_THRESHOLD.

Memory Controller Instruction Latency

An example of the instruction latency through the QDR II Memory Controller for write instructions is shown in Fig-

ure 78. For this example, it is assumed that the clock from the FPGA logic to the Memory Controller

(F_MC_WCLK) is synchronized to the K clock to the external memory. If these clocks are not synchronous, then

the latency may vary.

Figure 78. ORSPI4 QDR II Memory Controller – FPGA to External Memory Latency Example

The latency for read instructions is the same given the same clock relationship conditions.

Memory Controller Status Reporting

The following status or alarms will be reported to the user through software register bits:

• Data length mismatch from the write controller state machine. This alarm bit will be set if a block of data read

from the write data FIFO does not match the data length from its associated instruction.

• Data-instruction coherency error. This alarm bit will be set if the ID ﬁeld in write data and its associated write

instruction do not match.

• Write data, Read data FIFO overrun and underrun errors.

Clocking Schemes and Timing Diagrams- Memory Controller

The Memory Controller Unit requires three clocks:

• MC_WCLK from the FPGA, which controls the FPGA-side accesses to the Write Instruction and Write Data

F_MC_WCLK =

External Memory K Clock

F_MC_WDFIFO_WE

F_MC_WD(73:72)

F_MC_WD(71:0)

F_MC_WIFIFO_WE

F_MC_WI(25:24)

F_MC_WI(23:18)

F_MC_WI(17:0)

External Memory W#

D0-0

...

D0-31

D*32

2 K clock cycles

instruction latency

External Memory K Clock

Internal

FPGA

Logic

Memory

Controller

Interface

ORSPI4

External

Memory

Interface

ORSPI4 Datasheet(PDF) 142 Page - Lattice Semiconductor

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