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ADP5520 Datasheet(PDF) 30 Page - Analog Devices |
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ADP5520 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 40 page ![]() ADP5520 Rev. 0 | Page 30 of 40 Bit Mnemonic R/W Description 1 D1_IN_IEN R/W 0 = prevents D1 input from generating interrupts on nINT. 1 = allows D1 input to generate interrupts on nINT. 0 D0_IN_IEN R/W 0 = prevents D0 input from generating interrupts on nINT. 1 = allows D0 input to generate interrupts on nINT. Table 36. Register 0x1C, GPIO Interrupt Status (GPIO_INT_STAT) Bit Mnemonic R/W Description 7 D7_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D7_IN. Bit cleared when read twice. 6 D6_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D6_IN. Bit cleared when read twice. 5 D5_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D5_IN. Bit cleared when read twice. 4 D4_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D4_IN. Bit cleared when read twice. 3 D3_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D3_IN. Bit cleared when read twice. 2 D2_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D2_IN. Bit cleared when read twice. 1 D1_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D1_IN. Bit cleared when read twice. 0 D0_IN_ISTAT R 0 = no interrupt detected. 1 = interrupt condition detected on D0_IN. Bit cleared when read twice. Table 37. Register 0x1D, GPIO Interrupt Level Configuration (GPIO_INT_LVL) Bit Mnemonic R/W Description 7 D7_ILVL R/W 0 = interrupt generated when D7_IN is low. 1 = interrupt generated when D7_IN is high. 6 D6_ILVL R/W 0 = interrupt generated when D6_IN is low. 1 = interrupt generated when D6_IN is high. 5 D5_ILVL R/W 0 = interrupt generated when D5_IN is low. 1 = interrupt generated when D5_IN is high. 4 D4_ILVL R/W 0 = interrupt generated when D4_IN is low. 1 = interrupt generated when D4_IN is high. 3 D3_ILVL R/W 0 = interrupt generated when D3_IN is low. 1 = interrupt generated when D3_IN is high. 2 D2_ILVL R/W 0 = interrupt generated when D2_IN is low. 1 = interrupt generated when D2_IN is high. 1 D1_ILVL R/W 0 = interrupt generated when D1_IN is low. 1 = interrupt generated when D1_IN is high. 0 D0_ILVL R/W 0 = interrupt generated when D0_IN is low. 1 = interrupt generated when D0_IN is high. |
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