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ST72F321BAR9TCRE Datasheet(PDF) 69 Page - STMicroelectronics |
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ST72F321BAR9TCRE Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 247 page  ST72321Bxxx-Auto Power saving modes 69/247 Figure 24. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped. 8.4 Active Halt and Halt modes Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register) as shown in Table 26. WFI INSTRUCTION RESET INTERRUPT Y N N Y CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF 10 ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX(1) ON 256 OR 4096 CPU CLOCK CYCLE DELAY |
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