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ST72F321BAR9TCRE Datasheet(PDF) 86 Page - STMicroelectronics |
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ST72F321BAR9TCRE Datasheet(HTML) 86 Page - STMicroelectronics |
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86 / 247 page  Watchdog timer (WDG) ST72321Bxxx-Auto 86/247 10.9 Register description 10.9.1 Control register (WDGCR) WDGCR Reset value: 0111 1111 (7Fh) 7 654 32 10 WDGA T[6:0] RW RW Table 35. WDGCR register description Bit Name Function 7WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. 6:0 T[6:0] 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every 16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). Table 36. Watchdog timer register map and reset values Address (Hex.) Register label 7654 3210 002Ah WDGCR Reset Value WDGA 0 T6 1 T5 1 T4 1 T3 1 T2 1 T1 1 T0 1 |
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