AD9115-EBZ datasheet(13/48 Pages) AD

13 / 48 page

AD9114/AD9115/AD9116/AD9117

Rev. 0 | Page 13 of 48

PIN 1

INDICATOR

DB7

DB6

DB5

DB4

DVDDIO

DVSS

DVDD

DB3

DB2

DB1

23 QOUTP

24 RL1P

25 AVSS

26 AVDD

27 RL2N

28 IOUTN

29 IOUTP

30 RLIN

22 QOUTN

21 RL1N

TOP VIEW

(Not to Scale)

AD9115

NC = NO CONNECT

NOTES

1. THE HEAT SINK PAD IS CONNECTED TO AVSS AND

MUST BE SOLDERED TO THE GROUND PLANE.

EXPOSED METAL AT PACKAGE CORNERS IS

CONNECTED TO THIS PAD.

Figure 4. AD9115 Pin Configuration

Table 9. AD9115 Pin Function Description

Pin No.

Mnemonic

Description

1 to 4

DB[7:4]

Digital Inputs.

DVDDIO

Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).

DVSS

Digital Common.

DVDD

Digital Core Supply Voltage (1.8 V to 3.3 V).

8 to 10

DB[3:1]

Digital Inputs.

DB0 (LSB)

Digital Input (LSB).

12 to 15

No Connect. These pins are not connected to the chip.

DCLKIO

Data Input/Output Clock. Clock used to qualify input data.

CVDD

Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.

CLKIN

LVCMOS Sampling Clock Input.

CVSS

Sampling Clock Supply Voltage Common.

CMLQ

Q DAC Output Common-Mode Level.

RL1N

Load Resistor (62.5 Ω) to the CMLQ Pin.

QOUTN

Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.

QOUTP

Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.

RL1P

Load Resistor (62.5 Ω) to the CMLQ Pin.

AVSS

Analog Common.

AVDD

Analog Supply Voltage (1.8 V to 3.3 V).

RL2N

Load Resistor (62.5 Ω) to the CMLI Pin.

IOUTN

Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.

IOUTP

I DAC Current Output. Full-scale current is sourced when all data bits are 1s.

RLIN

Load Resistor (62.5 Ω) to the CMLI Pin.

CMLI

I DAC Output Common-Mode Level.

FSADJQ/AUXQ

Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor.

Auxiliary Q DAC Output When Internal On-Chip, RSET, is Enabled.

FSADJI/AUXI

Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor.

Auxiliary I DAC Output When Internal On-Chip, RSET, is Enabled.

REFIO

Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V

reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).

RESET/PINMD

Reset. In SPI mode, pulse RESET high to reset SPI registers to default values.

Pin Mode. A constant Logic 1 puts the device into pin mode.

AD9115-EBZ Datasheet(PDF) 13 Page - Analog Devices

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