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LX256VCFN4845 Datasheet(PDF) 38 Page - Lattice Semiconductor |
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LX256VCFN4845 Datasheet(HTML) 38 Page - Lattice Semiconductor |
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38 / 72 page  Lattice Semiconductor ispGDX2 Family Data Sheet 38 ispGDX2V/B/C, ispGDX2EV/EB/EC FIFO Internal Timing Parameter Description -3 -32 -35 -5 Units Min. Max. Min. Max. Min. Max. Min. Max. Routing Delays tFIFODATAIN FIFO Input Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFODATAOUT FIFO Output to I/O Core Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFORCLK Read Clock Input Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFOREN Read Clock Enable Input Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFOWCLK Write Clock Input Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFOWEN Write Clock Enable Input Delay — 0.00 — 0.00 — 0.00 — 0.00 ns Core Delays tFIFOCLKSKEW Global Read Clock to Write Clock Skew — 2.00 — 2.00 — 2.00 — 3.33 ns tFIFOEMPTY Read Clock to Empty Flag Delay — 1.30 — 1.80 — 1.80 — 3.00 ns tFIFOFULL Write Clock to Full Flag Delay — 1.30 — 1.80 — 1.80 — 3.00 ns tFIFORCEH Read Clock Hold after Read Clock Enable Time — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFORCES Read Clock Setup before Read Clock Enable Time — 1.50 — 1.50 — 1.50 — 2.50 ns tFIFORCLKO Read Clock to FIFO Out Delay — 0.50 — 0.50 — 0.50 — 0.83 ns tFIFORSTO Reset to Output Delay — 0.70 — 0.70 — 0.70 — 1.17 ns tFIFORSTPW Reset Pulse Width — 2.00 — 2.00 — 2.00 — 3.33 ns tFIFORSTR Reset Recovery Time — 1.20 — 1.50 — 2.00 — 3.33 ns tFIFOSTRD Write Clock to Start Read Flag Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFOTHRU Flow Through Delay — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFOWCEH Write Clock hold after Write Clock Enable Time — 2.00 — 2.00 — 2.00 — 3.33 ns tFIFOWCES Write Clock Setup before Write Clock Enable Time — 0.00 — 0.00 — 0.00 — 0.00 ns tFIFOWCLKH Write Data Hold after Write Clock Time — 0.50 — 0.50 — 0.70 — 1.17 ns tFIFOWCLKS Write Data Setup before Write Clock Time — 1.00 — 1.00 — 1.00 — 1.67 ns Timing v.2.2 |
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