LX256VCFN4845 datasheet(39/72 Pages) LATTICE

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Lattice Semiconductor

ispGDX2 Family Data Sheet

sysHSI Block Timing

Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on

a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N

input skew tolerance.

Figure 22. Receive Data Eye Diagram Template (Differential)

The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal

quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye

closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s

ability to transfer error-free data.

Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital

links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery

(CDR) portion of the ispGDX2 SERDES receiver is its ability to ﬁlter incoming signal jitter that is below the clock

recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data

error free, with eye openings signiﬁcantly less than that shown in Figure 22.

sysHSI Block AC Speciﬁcations

Operating Frequency Ranges

Symbol

Description

Mode

Test Condition

Min.

Max.

Units

fCLK

Reference Clock Frequency

SS:CAL

200

MHz

10B12B

MHz

8B10B

MHz

fSIN

Serial Input

SS:CAL

with eoSIN

400

800

Mbps

10B12B

with eoSIN

400

800

Mbps

8B10B

with eoSIN

400

800

Mbps

fSOUT

Serial Out

LVDS

CL = 5 pF, RL = 100 Ohms,

fCLK with no jitter

400

800

Mbps

1. fSIN (8B/10B and 10B/12B) 800Mbps limit applicable only to the fastest speed grade. Limit is 700Mbps for the lower speed grade.

2. fSIN and fSOUT speeds are supported at VCC and VCCP at 1.7V to 1.9V for ispGDX2C devices.

SIN

THD

200 mV Differential

+/- 100 mV Single Ended

Bit Time

TH : Optimum Threshold Crossing Jitter

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