MC13191 Technical Data, Rev. 1.6

Freescale Semiconductor

5

4.2

Receive Path Description

In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals

through two down-conversion stages. An Energy Detect can be performed based upon the baseband energy

integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD),

the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal,

determines the symbols and packets, and detects the data.

The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in

RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the

transmitted data which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured

over a 64 µs period after the packet preamble and stored in RAM.

The MC13191 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet

RAM. The MCU is notified that an entire packet has been received via an interrupt.

Figure 4 shows energy detection reported power versus input power.

NOTE

The 802.15.4 Standard accuracy and range limits are shown for reference.

Figure 4. Reported Power Level Versus Input Power for ED or LQI

4.3

Transmit Path Description

For the transmit path, the TX data that was previously stored in TX Packet RAM is retrieved, formed into

packets, spread, and then up-converted to the transmit frequency.

Because the MC13191 is used in packet mode, data is processed as an entire packet. The data is first loaded

into the TX buffer. The MCU then requests that the MC13191 transmit the data. The MCU is notified via

an interrupt when the whole packet has successfully been transmitted.

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Input Power Level (dBm)

802.15.4 Accuracy

and Range Requirements