M37542RSS datasheet(28/122 Pages) RENESAS

28 / 122 page

7542 Group

Rev.3.03

Jul 11, 2008

Page 28 of 117

REJ03B0006-0303

• Interrupt Request Generation, Acceptance, and Handling

Interrupts have the following three phases.

(i) Interrupt Request Generation

An interrupt request is generated by an interrupt source (ex-

ternal interrupt signal input, timer underflow, etc.) and the

corresponding request bit is set to “1”.

(ii) Interrupt Request Acceptance

Based on the interrupt acceptance timing in each instruction

cycle, the interrupt control circuit determines acceptance con-

ditions (interrupt request bit, interrupt enable bit, and interrupt

disable flag) and interrupt priority levels for accepting interrupt

requests. When two or more interrupt requests are generated

simultaneously, the highest priority interrupt is accepted. The

value of the interrupt request bit for an unaccepted interrupt

remains the same and acceptance is determined at the next

interrupt acceptance timing point.

(iii) Handling of Accepted Interrupt Request

The accepted interrupt request is processed.

Figure 25 shows the time up to execution in the interrupt process-

ing routine, and Figure 26 shows the interrupt sequence.

Figure 27 shows the timing of interrupt request generation, inter-

rupt request bit, and interrupt request acceptance.

• Interrupt Handling Execution

When interrupt handling is executed, the following operations are

performed automatically.

(1) Once the currently executing instruction is completed, an in-

terrupt request is accepted.

(2) The contents of the program counters and the processor sta-

tus register at this point are pushed onto the stack area in

order from 1 to 3.

1.High-order bits of program counter (PCH)

2.Low-order bits of program counter (PCL)

3.Processor status register (PS)

(3) Concurrently with the push operation, the jump address of the

corresponding interrupt (the start address of the interrupt pro-

cessing routine) is transferred from the interrupt vector to the

program counter.

(4) The interrupt request bit for the corresponding interrupt is set

to “0”. Also, the interrupt disable flag is set to “1” and multiple

interrupts are disabled.

(5) The interrupt routine is executed.

(6) When the RTI instruction is executed, the contents of the reg-

isters pushed onto the stack area are popped off in the order

from 3 to 1. Then, the routine that was before running interrupt

processing resumes.

As described above, it is necessary to set the stack pointer and

the jump address in the vector area corresponding to each inter-

rupt to execute the interrupt processing routine.

■ Notes on Interrupts

When setting the followings, the interrupt request bit may be set to

“1”.

•When switching external interrupt active edge

Related registers:

Interrupt edge selection register (address 003A16)

Timer X mode register (address 002B16)

Capture mode register (address 002016)

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

➀ Set the corresponding interrupt enable bit to “0” (disabled).

➁ Set the interrupt edge select bit (active edge switch bit, trigger

mode bit).

➂ Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

➃ Set the corresponding interrupt enable bit to “1” (enabled).

Main routine

Interrupt handling

routine

Interrupt request

generated

Interrupt request

acceptance

Interrupt routine

starts

Interrupt sequence

7 cycles

0 to 16* cycles

7 to 23 cycles

* When executing DIV instruction

Stack push

Vector fetch

Fig. 25 Time up to execution in interrupt routine

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