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R8C2C Datasheet(PDF) 115 Page - Renesas Technology Corp

Part # R8C2C
Description  RENESAS MCU R8C FAMILY / R8C/2x SERIES
PDF  615 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R8C2C Datasheet(HTML) 115 Page - Renesas Technology Corp

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R8C/2C Group, R8C/2D Group
9. Bus
Rev.2.00
Dec 05, 2007
Page 94 of 585
REJ09B0339-0200
9.
Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/2C Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/2D Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations and Table 9.4 lists Access Units and Bus Operations of SFR (address
0200h to 02FFh).
Table 9.3
Access Units and Bus Operations
Table 9.1
Bus Cycles by Access Space of the R8C/2C Group
Access Area
Bus Cycle
SFR (address 0000h to 01FFh)
2 cycles of CPU clock
SFR (address 0200h to 02FFh)
3 cycles of CPU clock
ROM/RAM
1 cycle of CPU clock
Table 9.2
Bus Cycles by Access Space of the R8C/2D Group
Access Area
Bus Cycle
SFR (address 0000h to 01FFh)/Data flash 2 cycles of CPU clock
SFR (address 0200h to 02FFh)
3 cycles of CPU clock
Program ROM/RAM
1 cycle of CPU clock
Area
SFR (address 0000h to 01FFh), data flash
Even address
Byte access
ROM (program ROM), RAM
Odd address
Byte access
Even address
Word access
Odd address
Word access
CPU clock
Data
Data
Data
Even
Even
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
CPU
clock
Data
Address
Data
Data
Odd
Odd
Data
Even
Even + 1
Data
Data
Odd
Odd + 1
Data
Data
Even
Even + 1
Data
Data
Odd
Odd + 1
Data



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