R8C2C datasheet(151/615 Pages) RENESAS

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R8C/2C Group, R8C/2D Group

12. Interrupts

Rev.2.00

Dec 05, 2007

Page 130 of 585

REJ09B0339-0200

12.1.6

Interrupt Control

The following describes enabling and disabling the maskable interrupts and setting the priority for

acknowledgement. The explanation does not apply to nonmaskable interrupts.

Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or

disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control

Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, TRD0IC, TRD1IC,

SSUIC, and IICIC and Figure 12.5 shows the INTiIC Register.

Figure 12.3

Interrupt Control Register

Interrupt Control Register(2)

Address

After Reset

004Ah

XXXXX000b

004Bh

XXXXX000b

004Ch

XXXXX000b

004Dh

XXXXX000b

0050h

XXXXX000b

0051h

XXXXX000b

0052h

XXXXX000b

0053h

XXXXX000b

0054h

XXXXX000b

0056h

XXXXX000b

0058h

XXXXX000b

TRFIC

005Bh

XXXXX000b

CMP0IC

005Ch

XXXXX000b

005Eh

XXXXX000b

005Fh

XXXXX000b

Bit Symbol

Function

NOTES:

Only 0 can be w ritten to the IR bit. Do not w rite 1.

0 : Requests no interrupt

1 : Requests interrupt

RW(1)

—

(b7-b4)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

b2 b1 b0

0 0 0 : Level 0 (interrupt disable)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL1

ILVL2

Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.

Refer to 12.6.5 Changing Interrupt Control Register Contents.

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Bit Name

Interrupt priority level select bits

Interrupt request bit

ILVL0

CAPIC

S1TIC

S1RIC

ADIC

TREIC

TRBIC

S2TIC

S2RIC

TRAIC

KUPIC

CMP1IC

S0TIC

S0RIC

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