M32C83T datasheet(337/527 Pages) RENESAS

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Page 314

21. Intelligent I/O (Group 2 Communication Function)

)

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21.5.2 IEBus Mode (Group 2)

Table 21.36 lists specifications of IEBus mode. Table 21.37 lists registers to be used and settings.

Tables 21.38 to 21.40 lists pin settings.

Table 21.36 IEBus Mode Specifications

Item

Specification

Transfer Data Format

• Transfer data length: 1 to 8 bits

Transfer Clock

• When the CKDIR bit in the G2MR register is set to "0" (internal clock) :

n : setting value of the G2PO0 register, 000016 to FFFF16.

The G2PO0 register determines bit rate and the transfer clock is generated

in phase-delayed waveform output mode of the channel 2 waveform generation

function.

The G2PO2 register = (n+2)/2(1)

• When the CKDIR bit is set to "1" (external clock) : input from the ISCLK2 pin(2)

Transmit Start Condition

To start transmitting, the following conditions are required :

• Set the TE bit in the G2CR register to "1" (transmit enable)

• Write data to G2TB register

Receive Start Condition

To start receiving, the following requirements must be met:

• Set the RE bit in the G2CR register to "1" (receive enable)

• Set the TE bit in the G2CR register to "1" (transmit enable)

• Write data to the G2TB register

Interrupt Request

• While transmitting, the following conditions can be selected to set the SIO2TR bit in

the IIO6IR register to "1" (see Figure 10.14):

- The IRS bit in the G2MR register is set to "0" (no data in the G2TB register):

when data is transferred to the transmit register from the G2TB register (transmis-

sion started)

- The IRS bit is set to "1" (transmission completed):

when data transfer from the transmit register to the G2TO register is completed

• While receiving, the following condition can be selected to set the SIO2RR bit in the

IIO5IR register to "1" (see Figure 10.14):

when data is transferred from receive register to the G2RB register (data reception

is completed)

Error Detection

Overrun error(3)

This error occurs when receiving the j bit (j=1 to 8) of the next data (transfer data

length: j bits) before reading the G2RB register

Selectable Function

• LSB first/MSB first select

Select either bit 0 or bit 7 to transmit/receive data

• ISTxD2 and ISRxD2 I/O polarity inverse

ISTxD2 pin output and ISRxD2 pin input levels are inversed

• Data transfer bit length

Select from 1 to 8 bits

NOTES:

1. The transfer clock must be fBT2 divided by six or more when both transfer clock and transfer data are

transmitted. Under conditions other than this, the transfer clock must be fBT2 divided by 20 or more.

2. Transfer clock must be input fBT2 divided by 20 or more.

3. When an overrun error occurs, the G2RB register is indeterminate.

fBT2

2(n+2)

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