M32C83T datasheet(333/527 Pages) RENESAS

333 / 527 page

Page 310

21. Intelligent I/O (Group 2 Communication Function)

)

(

21.5.1 Variable Clock Synchronous Serial I/O Mode (Group 2)

In variable clock synchronous serial I/O mode, data is transmitted and received using the transfer clock.

The length of data transferred is selected from 1 to 8 bits. Table 21.30 lists specifications of the group 2

variable clock synchronous serial I/O mode. Table 21.31 lists registers to be used and their settings.

Tables 21.32 to 21.35 lists pin settings. Figure 21.46 shows an example of a transmit and receive

operation.

Table 21.30 Variable Clock Synchronous Serial I/O Mode Specifications (Group 2)

Item

Specification

Transfer Data Format

• Transfer data length : 1 to 8 bits

Transfer Clock(1)

• When the CKDIR bit in the G2MR register is set to "0" (internal clock) :

n : setting value of the G2PO0 register 000016 to FFFF16

The G2PO0 register determines bit rate and the transfer clock is generated in

phase-delayed waveform output mode of the channel 2 waveform generation func-

tion.

• When the CKDIR bit is set to "1" (external clock) : input from the ISCLK2 pin(2)

Transmit Start Condition

• To start transmitting, the following conditions are required :

- Set the TE bit in the G2CR register to "1" (transmit enable)

- Write data to the G2TB register

Receive Start Condition

• To start receiving, the following conditions are required :

- Set the RE bit in the G2CR register to "1" (receive enable)

- Set the TE bit in the G2CR register to "1" (transmit enable)

- Write data to the G2TB register

Interrupt Request

• While transmitting, one of the following conditions can be selected to set the

SIO2TR bit in the IIO6IR register to "1" (see Figure 10.14):

- The IRS bit in the G2MR register is set to "0" (no data in the G2TB register):

when data is transferred from the G2TB register to the transmit register.

- The IRS bit is set to "1" (reception completed):

when data transfer from the transmit register is completed

• While receiving, the following condition can be selected to set the SIO2RR bit in the

IIO5IR register to "1" (interrupt request) (see Figure 10.14):

when data is transferred from the receive register to the G2RB register (data recep-

tion is completed)

Error Detection

Overrun error(3)

This error occurs when receiving the j bit (j=1 to 8) of the next data (transfer data

length: j bits) before reading the G2RB register

Selectable Function

• LSB first/MSB first

Select either bit 0 or bit 7 to transmit/receive data

• ISTxD2 and ISRxD2 I/O polarity inverse

ISTxD2 pin output level and ISRxD2 pin input level are inversed

• Data transfer bit length

Select from 1 to 8 bits

NOTES:

1. The transfer clock must be fBT2 divided by six or more when both transfer clock and transfer data are

transmitted. Under conditions other than this, the transfer clock must be fBT2 divided by 20 or more.

2. Transfer clocks must be fBT2 divided by 20 or more.

3. When an overrun error occurs, the G2RB register is indeterminate.

fBT2

2(n+2)

M32C83T Datasheet(PDF) 333 Page - Renesas Technology Corp

M32C83T Datasheet(HTML) 333 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL