M32C83T datasheet(330/527 Pages) RENESAS

330 / 527 page

Page 307

21. Intelligent I/O (Group 0, 1 Communication Function)

)

(

Figure 21.43 G2MR and G2CR Register

GMD0

GMD1

CKDIR

(b5 - b3)

Communication Mode

Select Bit

UFORM

IRS

Internal/External Clock

Select Bit

Transfer Format

Select Bit

Transmit Interrupt

Cause Select Bit

0 : Internal clock

1 : External clock

0 : LSB first

1 : MSB first

0 : No data is in the transmit buffer

1 : Transmission is completed

: Communication unit is reset

(The OER bit is set to "0")(1)

: Clock synchronous serial I/O

mode(2)

: IE mode(2)

: Do not set to this value

Group 2 SI/O Communication Mode Register

Symbol

Address

After Reset

G2MR

016A16

00XX X0002

Bit Name

Function

Bit

Symbol

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

NOTES:

1. Run the base timer clock for one or more cycles after the GMD1 to GMD0 bits are set to "002"

(communication unit reset).

2. Set the GMD1 to GMD0 bits to "012" (clock synchronous serial I/O mode) or "102" (IE mode) while

the base timer clock is stopped.

Group 2 SI/O Communication Control Register

Symbol

Address

After Reset

G2CR

016B16

0000 X0002

Bit Name

Function

Bit

Symbol

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

TXEPT

Transmit Enable Bit

(b3)

IPOL

OPOL

Receive Complete

Flag

Transmit Buffer

Empty Flag

Receive Enable Bit1

0 : No data is in the G2RB register

1 : Data is in the G2RB register

0 : Data is in the G2TB register

1 : No data is in the G2TB register

Transmit Register

Empty Flag

0 : Data is in the transmit register

(during transmission)

1 : No data is in the transmit register

(transmission is completed)

0 : Transmit disabled

1 : Transmit enabled

0 : Receive disabled

1 : Receive enabled

ISRxD Input Polarity

Switch Bit(1)

ISTxD Output Polarity

Switch Bit

0 : No inverse

1 : Inverse

0 : No inverse

1 : Inverse

NOTES:

1. The group 2 base timer may be reset when rewriting the RE or IPOL bit. To avoid resetting, set the

RST2 bit in the G2BCR1 register to "0" (no base timer reset by a reset request from the

communication function).

M32C83T Datasheet(PDF) 330 Page - Renesas Technology Corp

M32C83T Datasheet(HTML) 330 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL