M32C83T datasheet(327/527 Pages) RENESAS

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21. Intelligent I/O (Group 0, 1 Communication Function)

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Table 21.28 HDLC Processing Mode Specifications (Continued)

Item

Specification

Data Processing

The following conditions are required to start transmit data processing:

Start Conditions

• The TE bit in the GiCR register is set to "1" (transmit enable)

• Data is written to the GiTB register

The following conditions are required to start receive data processing:

• The RE bit in the GiCR register is set to "1" (receive enable)

• Data is written to the GiRI register

Interrupt Request(3)

During transmit data processing,

(1) One of the following conditions can be selected to set the GiTOR bit in the interrupt

request register to "1" (interrupt request) (see Figure 10.14)

_ When the IRS bit in the GiMR register is set to "0" (no data in the GiTB register)

and data is transferred from the GiTB register to the transmit register (transmit start)

_ When the IRS bit is set to "1" (transmission completed) and data transfer from

the transmit register to the GiTO register is completed

(2) When data, which is already converted to HDLC data, is transferred from the

receive register of the GiTO register to the transmit buffer, the GiTOR bit is set

to "1"

During received data processing,

(1) When data is transferred from the GiRI register to the GiRB register (reception

completed), the GiRIR bit is set to "1" (See Figure 10.14)

(2) When received data is transferred from the receive buffer of the GiRI register to

the receive register, the GiRIR bit is set to "1"

(3) When the GiTB register is compared to the GiCMPj register (j=0 to 3), the SRTiR

bit is set to "1"

NOTES:

1. Set the CRCV bit and ACRC bit in the GiEMR register to "1".

2. The CRC calculation circuit is reset after the GiRCRC register stores CRC data.

3. See Figure 10.14 for details on the GiTOR bit, GiRIR bit and SRTiR bit.

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