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M32C83T Datasheet(PDF) 323 Page - Renesas Technology Corp |
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M32C83T Datasheet(HTML) 323 Page - Renesas Technology Corp |
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323 / 527 page ![]() Page 300 8 8 4 f o 6 0 0 2 , 1 3 . n a J 1 3 . 1 . v e R 1 3 1 0 - 4 3 0 0 B 9 0 J E R 21. Intelligent I/O (Group 0, 1 Communication Function) ) T 3 8 / C 2 3 M , 3 8 / C 2 3 M ( p u o r G 3 8 / C 2 3 M Table 21.23 Registers to be Used and Settings Register Bit Function GiBCR0 BCK1 to BCK0 Set to "112" DIV4 to DIV0 Select divide ratio of count source IT Set to "0" GiBCR1 7 to 0 Set to "0001 00102" GiPOCR0 7 to 0 Set to "0000 01112" GiPOCR2 7 to 0 Set to "0000 01102" GiPOCR3 7 to 0 Set to "0000 00102" GiTMCR2 7 to 0 Set to "0000 00102" GiPO0 15 to 0 Set bit rate = transfer clock frequency GiPO3 15 to 0 Set to a value smaller than the GiPO0 register GiFS FSC3 to FSC0 Set to "01002" GiFE IFE3 to IFE0 Set to "11012" GiMR GMD1 to GMD0 Set to "002" CKDIR Set to "0" STPS Select stop bit length UFORM Select LBS first or MSB first IRS Select how the receive interrupt is generated GiCR TI Transmit buffer empty flag TXEPT Transmit register empty flag RI Receive complete flag TE Set to "1" to enable transmission RE Set to "1" to enable reception IPOL Set to "1" OPOL Set to "1" GiTB 7 to 0 Write data to be transmitted GiRB 15 to 0 Received data and error flag are stored i = 0 to 1 fBTi 2 x (setting value + 2) |
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