M32C83T datasheet(326/527 Pages) RENESAS

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21. Intelligent I/O (Group 0, 1 Communication Function)

)

(

21.4.3 HDLC Data Processing Mode (Group 0 and 1)

In HDLC data processing mode, bit stuffing, flag detection, abort detection and CRC calculation are

available for HDLC control. The channel 0 and 1 are used to generate the transfer clock. No pins are

used.

To convert data, data to be transmitted is written to the GiTB register (i=0,1) and the data conversion

result is restored after data conversion. If any data are in the GiTO register after data conversion, the

conversion is terminated. If no data is in the GiTO register, bit stuffing processing is executed regardless

of there being no data in the transmit output buffer. A CRC value is calculated every time one bit is

converted. If no data is in the GiRI register, received data conversion is terminated.

Table 21.28 list specifications of the HDLC data processing mode. Table 21.29 lists registers to be used

and their settings.

Table 21.28 HDLC Processing Mode Specifications

Item

Specification

Input Data Format

8-bit data fixed, bit alignment is optional

Output Data Format

8-bit data fixed

Transfer Clock

When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :

n : setting value of the GiPO0 register 000016 to FFFF16

• The GiPO0 register determines bit rate.

The transfer clock is generated in phase-delayed waveform output mode of the

channel 1 waveform generation function.

When the RSHTE bit in the GiERC register is set to "1" (reception shift operation

enabled), the transfer clock is generated in the receiver

I/O Method

• While transmitting,

value set in the GiTB register is converted in HDLC data processing mode and

transferred to the GiTO register

• While receiving,

value set in the GiRI register is converted in HDLC data processing mode and

transferred to the GiRB register. The value in the GiRI register is also transferred to

the GiDR register (received data register).

Bit Stuffing

While transmitting, "0" following five consecutive "1" is inserted.

While receiving, "0" following five consecutive "1" is deleted.

Flag Detection

Write the flag data "7E16" to the GiCMP3 register to use the special communication

interrupt (the SRTiR bit in the IIO4IR register)

Abort Detection

Write the masked data "0116" to the GiMSKk(k=0, 1) register

CRC

The CRC1 to CRC0 bits are set to "112" (X16+X12+X5+1)

The CRCV bit is set to "1" (set to "FFFF16")

• While transmitting, CRC calculation result is stored into the GiTCRC register.

The TCRCE bit in the GiETC register is set to "1" (transmit CRC used).

The CRC calculation result is reset when the TE bit in the GiCR register is set to "0"

(transmit disabled)(1).

• While receiving, CRC calculation result is stored into the GiRCRC register.

The RCRCE bit in the GiERC register is set to "1" (receive CRC used).

The CRC calculation result is reset by comparing the flag data "7E16" and matching

the result with the value in the GiCMP3 register. The ACRC bit in the GiEMR regis-

ter is set to "1" (CRC reset)(2)

fBTi

n+2

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