M32C83T datasheet(322/527 Pages) RENESAS

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21. Intelligent I/O (Group 0, 1 Communication Function)

)

(

21.4.2 Clock Asynchronous Serial I/O Mode (UART) (Groups 0 and 1)

In clock asynchronous serial I/O mode (UART), data is transmitted at a desired bit rate and in a desired

transfer data format. Table 21.22 lists specifications of UART mode groups 0 and 1. Table 21.23 lists

registers to be used and their settings. Tables 21.24 to 21.27 list pin settings. Figure 21.40 shows an

example of transmit operation. Figure 21.41 shows an example of receive operation.

Table 21.22 UART Mode Specifications

Item

Specification

Transfer Data Format

• Character Bit (transfer data) :

8 bits long

• Start bit :

1 bit long

• Stop bit :

select length from 1 bit or 2 bits

Transfer Clock(1, 2)

When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :

n : setting value of the GiPO0 register, 000016 to FFFF16.

• The GiPO0 register determines the bit rate.

Transmit clock is generated in phase-delayed waveform output mode of the chan-

nel 3 waveform generation function.

Receive clock is generated with the channel 2 time measurement function.

Transmit Start Condition

Set the registers associated with the waveform generation function, the GiMR register and

GiERC register. Then, set as written below after at least one transfer clock cycle.

• Set the TE bit in the GiCR register to "1" (transmit enable)

• Set the TI bit in the GiCR register to "0" (data in the GiTB register)

Receive Start Condition

Set the registers associated with the waveform generation function, the GiMR register and

GiERC register. Then, set as written below after at least one transfer clock cycle.

• Set the RE bit in the GiCR register to "1" (receive enable)

• Detect the start bit

Interrupt Request

• While transmitting, one of the following conditions can be selected to set the SIOiTR

bit to "1" (see Figure 10.14):

_ The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and

data is transferred to the transmit register from the GiTB register.

_ The IRS bit is set to "1" (transmission completed) and data transfer from the

transmit register is completed

• While receiving, the following condition can be selected to set the SIOiRR bit to "1"

(see Figure 10.14) :

Data is transferred from the receive register to the GiRB register (data reception is

completed)

Error detection

• Overrun error(3)

This error occurs when the final stop bit of the next data is received before reading

the GiRB register

• Framing Error

This error occurs when the number of the stop bits set is not detected

Selectable function

• Stop bit length

The length of the stop bit is selected from 1 bit or 2 bits

• LSB first/MSB first

Select either bit 0 or bit 7 to transmit/receive data

NOTES:

1. The transfer clock must be fBTi divided by six or more.

2. Set the GiPOCR2 register and the GiTMCR2 register.

3. When an overrun error occurs, the GiRB register is indeterminate.

fBTi

2(n+2)

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