M32C83T datasheet(319/527 Pages) RENESAS

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21. Intelligent I/O (Group 0, 1 Communication Function)

)

(

21.4.1 Clock Synchronous Serial I/O Mode (Groups 0 and 1)

In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. When the

internal clock is selected as the transfer clock, the channel 0 and channel 3 waveform generation func-

tions generate the internal clock. ISTxDi (i=0, 1), ISCLKi, and ISRxDi share pins with INPCi0 to INPCi2

and OUTCi0 to OUTCi2.

Table 21.16 lists specifications of clock synchronous serial I/O mode. Table 21.17 lists registers to be

used and their settings. Tables 21.18 to 21.21 list pin settings. Figure 21.39 shows an example of a

transmit and receive operation.

Table 21.16 Clock Synchronous Serial I/O Mode Specifications (Groups 0 and 1)

Item

Specification

Transfer Data Format

Transfer data :

8 bits long

Transfer Clock(1, 2)

When the CKDIR bit in the GiMR register (i=0, 1) is set to "0" (internal clock) :

n : setting value of the GiPO0 register, 000016 to FFFF16

• The GiPO0 register determines the bit rate and the transfer clock is generated in

phase-delayed waveform output mode by the channel 3 waveform generation func-

tion.

When the CKDIR bit is set to "1" (external clock) : input from the ISCLKi pin

Transmit Start Condition

Set registers associated with the waveform generation function, the GiMR register and the

GiERC register. Then set as written below after at least one transfer clock cycle:

• Set the TE bit in the GiCR register to "1" (transmit enable)

• Set the TI bit in the GiCR register to "0" (data in the GiTB register)

Receive Start Condition

Set registers associated with the waveform generation function, the GiMR register and

GiERC register. Then set as written below after at least one transfer clock cycle:

• Set the RE bit in the GiCR register to "1" (receive enable)

• Set the TE bit to "1" (transmit enable)

• Set the TI bit to "0" (data in the GiTB register)

Interrupt Request

• While transmitting, one of the following conditions can be selected to set the SIOiTR

bit to "1" (see Figure 10.14):

_ The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and data

is transferred to the transmit register from the GiTB register

_ The IRS bit is set to "1" (transmission completed) and data transfer from the

transmit register is completed

• While receiving, the following condition can be selected to set the SIOiRR bit to "1"

(see Figure 10.14):

Data is transferred from the receive register to the GiRB register

Error Detection

Overrun error(3)

This error occurs when the 8th bit of the next data is received before reading the GiRB register

Selectable Function

• LSB first/MSB first

Select either bit 0 or bit 7 to transmit/receive data

• ISTxDi and ISRxDi I/O polarity inverse

ISTxDi pin output level and ISRxDi pin input level are inversed

NOTES:

1. The transfer clock must be fBTi divided by six or more.

2. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive

shift operation enabled).

3. When an overrun error occurs, the GiRB register is indeterminate.

When the OPOL bit in the GiCR register is set to "0" (no ISTxDi output polarity inversed), the ISTxDi pin

outputs an "H" signal after selecting operation mode until transfer starts. When the OPOL bit is set to "1",

the ISTxDi pin outputs an "L" signal.

fBTi

2(n+2)

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