M32C83T datasheet(346/527 Pages) RENESAS

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Page 323

21. Intelligent I/O (Group 3 Communication Function)

)

(

Figure 21. 51 Transmit and Receive Operation (16-bit Length)

n+2

Base Timer 3

The base timer is reset by the channel 0

waveform generation function

ISRxD3 pin input

(received data)

ISTxD3 pin output

(data to be transmitted)

ISCLK3 pin output

(transmit clock in the

channel 2 WG function)

SIO3TR bit

when IRS=0

(no data in the

transmit buffer)

SIO3TR bit

when IRS=1

(transmission completed)

Write to the G3TB register

The above timing applies under the following settings.

• The CKDIR bit in the G3MR register is set to "0" (internal clock)

• The UFORM bit in the G3MR register is set to "0" (LSB first)

• The IPOL bit and OPOL bit in the G3CR register are set to "0" (no inverse)

• The TLD bit in the G3CR register is set to "1" (16 bits long)

n : Setting value of the G3PO0 register

m : Setting value of the G3PO2 register

SIO3TR bit : Bit in the IIO10IR register

SIO3RR bit : Bit in the IIO9IR register

IRS bit

: Bit in the G3MR register

Bit 1

Bit 2

Bit 14

Bit 0

Bit 15

Bit 1

Bit 2

Bit 14

Bit 0

Bit 15

SIO3RR bit

Write "0" by program if setting to "0"

Write "0" by program

if setting to "0"

Write "0" by program

if setting to "0"

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