M32C83T datasheet(347/527 Pages) RENESAS

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Page 324

22. CAN Module

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22. CAN Module

The CAN (Controller Area Network) module incorporated in the M32C/83 group is a Full CAN module,

compatible with CAN Specification 2.0 Part B. Table 22.1 lists specifications of the CAN module.

Table 22.1 CAN Module Specifications

Item

Specification

Protocol

CAN Specification 2.0 Part B

Message Slots

16 slots

Polarity

Dominant: "L"

Recessive: "H"

Acceptance Filter

Global mask: 1 mask (for message slots 0 to 13)

Local mask: 2 masks (for message slots 14 and 15 respectively)

Baud Rate

Baud rate =

--- Max. 1 Mbps

Tq clock cycle =

Tq per bit = SS + PTS +PBS1+PBS2

Tq:

Time quantum

BRP: Setting value in the C0BRP and C1BRP registers, 1-255

SS:

Synchronization Segment; 1 Tq

PTS: Propagation Time Segment; 1 to 8 Tq

PBS1: Phase Buffer Segment 1; 2 to 8 Tq

PBS2: Phase Buffer Segment 2 ; 2 to 8 Tq

Remote Frame Automatic

Message slot that receives the remote frame transmits the data frame

Answering Function

automatically

Time Stamp Function

Time stamp function with a 16-bit counter. Count source can be selected

from the CAN bus bit clock divided by 1, 2, 3 or 4.

BasicCAN Mode

BasicCAN function can be used with the CANi message slots 14 and 15.

Transmit Abort Function

Transmit request is aborted

Loopback Function

Frame transmitted by the CAN module is received by the same CAN module

Forcible Error Active

The CAN module is forced into an error active state

Clear Function

NOTES:

1. Use an oscillator with maximum 1.58% oscillation tolerance.

Figure 22.1 shows a block diagram of the CAN module. Figure 22.2 shows CANi message slot buffer (the

message slot buffer) (i=0,1) and CANi message slot (the message slot) j (j=0 to 15). Table 22.2 lists pin

settings of the CAN module.

The message slot cannot be accessed directly from the CPU. Allocate the message slot j to be used to the

message slot buffer 0 or 1. The message slot j is accessed via the message slot buffer address. The

CiSBS register selects the message slot j to be allocated. Figure 22.2 shows the 16-byte message slot

buffer and message slot.

Tq clock cycle x Tq per bit

BRP + 1

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